a) Field of the Invention
The invention relates to clock recovery by a demodulator in a data communication system.
b) Description of the Related Art
A conventional clock recovery circuit to recovers a clock by determining a phase component of an input signal's clock by Fourier transformation and performing a reverse modulation of the determined phase component. FIG. 12 shows an example of configuration of a conventional clock recovery circuit, which is disclosed in, for example, Japanese Patent Laid-Open Publication No. Hei 6-232933, "Clock Recovery Circuit". In FIG. 12, reference numeral 101 denotes an input terminal, 103 and 104 multipliers for multiplying an input signal by a twiddle factor (cos or -sin component) for the Fourier transform, 105 and 106 low pass filters for averaging outputs from the multiplier 103 or 104, 107 a multiplier for multiplying output from the low pass filter 105 by a twiddle factor, 108 a multiplier for multiplying output from the low pass filter 106 by a twiddle factor, 109 an adder for adding outputs from the multiplier 107 and the multiplier 108, 110 is a signal generating circuit for preparing a twiddle factor, and 111 indicates an output terminal for a recovered clock output from the adder 109.
The operation of a known method will be described with reference to FIG. 12. To simplify description, the number of samples per symbol will be defined as N=4, and the Fourier transform referred to in this specification is the discrete Fourier transform (hereinafter called "DFT", including FFT). The input signal entered into the clock recovery circuit is a signal prepared by having a received signal undergo non-linear processing to facilitate the extraction of a clock component.
The multiplier 103 and the multiplier 104 multiply an input signal by a twiddle factor. As the twiddle factor, the multiplier 103 uses cos component, while the multiplier 104 uses -sin component. Assuming that the number of samples per symbol of the input signal is N, the cos and -sin components output from the signal generating circuit 110 are given by the respective following equations (1) and (2). EQU cos (2 .pi.n/N) (where n=0, 1, 2, . . . ) (1) EQU -sin (27 .pi.n/N) (where n=0, 1, 2, . . . ) (2)
Then, assuming that the input signal is expressed as follows: EQU X(n) (3)
output X.sub.1 (n) from the multiplier 103 and output X.sub.2 (n) from the multiplier 104 are expressed by the following equations (4) and (5), respectively. EQU X.sub.1 (n)=X(n).multidot.cos (2 .pi.n/N) (4) EQU X.sub.2 (n)=X(n).multidot.(-sin (2 .pi.n/N)) (5)
And, the following equation (6) is applied to the equations (4) and (5) to obtain the following equations (7) and (8): ##EQU1##
The low pass filter 105 and the low pass filter 106 average the output from the multiplier 103 and the output from the multiplier 104 respectively to remove noise components.
The conventional DFT performs processing on a single sample basis to simplify a processing structure, namely a hardware structure, and does not perform processing on a symbol basis.
The multiplier 107 multiplies the output from the low pass filter 105 by the cos component, and the multiplier 108 multiplies the output from the low pass filter 106 by the -sin component. The adder 109 adds the output from the multiplier 107 and that from the multiplier 108 to prepare a recovered clock. When it is assumed that N=4, the cos component and the -sin component with respect to a single symbol are given as follows: EQU {1, 0, -1, 0} (9) EQU {0, -1, 0, 1} (10)
The output from the adder is obtained by alternately selecting the output from the multiplier 107 and that from the multiplier 108 and adding a code of the input signal in compliance with a code of the twiddle factor.
Accordingly, when it is assumed that the output from the low pass filter 105 is Y.sub.1 (n) and that from the low pass filter 106 is Y.sub.2 (n), the recovered clock may have a sequence such as: EQU {Y.sub.1 (n), -Y.sub.2 (n+1), -Y.sub.1 (n+2), Y.sub.2 (n+3), Y.sub.1 (n+4), -Y.sub.2 (n+5), . . . }.
Since the low pass filter is an averaging filter, it is necessary to increase the number of averaging symbols in order to improve the accuracy of the recovered clock. However, when the number of averaging symbols is increased, the number of bits also increases, and circuit scale is enlarged. Therefore, generally when averaging, either a moving average is performed as shown in FIG. 13 or a forgetting factor is multiplied while cumulative adding as shown in FIG. 14 to prevent the circuit scale from becoming large. If the input signal does not have a clock component, the input value of the low pass filter becomes {0, 0}, the output value from the low pass filter becomes small, and an estimated clock phase tends to be affected by noise.